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DTSTART:19700308T020000
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DTSTAMP:20260202T201224Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T165600
DTEND;TZID=America/Chicago:20251117T165700
UID:submissions.supercomputing.org_SC25_sess553_job302@linklings.com
SUMMARY:System Validation Engineer Lead
DESCRIPTION:Mission: \nTest and validate silicon and systems for the most 
 advanced AI accelerator on the market.\n\nResponsibilities & opportunities
  in this role:\nNew silicon bring up, create validation plan, & perform sy
 stem validation on all aspects in a lead role\nValidation of HSIO and LSIO
  IPs\nDrive ATE to system correlation efforts during NPI stage\nPerform sc
 ripting and test data processing to extract meaningful signals\nDevelop an
 d integrate software test applications for effective product stress and SL
 T screening.\nCollaborate with software teams to evaluate system performan
 ce and HW/SW interaction under various conditions.\nEnable automation to e
 xtract key validation and characterization data collected across PVT\nRoot
  cause analysis and RMA processing\nMentor Junior Engineers when the proje
 ct need arises\nExperience in Post Silicon Electrical Validation of server
  processors (if server processor is too specific, you can remove server)\n
 \nIdeal candidates have/are:\nProven driver and leader of a full system va
 lidation from end to end (silicon out to production start) with attention 
 to detail and a passion for root causing issues\nSilicon validation experi
 ence, preferably in the area of HSIO, LSIO, Logic and Memory. BE or ME Gra
 duate\nExperience in system marginality validation\nGood understanding of 
 lab equipment and measurement techniques for high-speed interfaces. High s
 peed scopes, probes, spectrum analyzers, BERTs.\nStrong understanding of E
 lectrical Engineering fundamentals\nStrong understanding of Firmware and a
 ble to debug and create new test cases\nKnowledge of board and package des
 ign, signal integrity and power integrity a plus\nSoftware proficiency for
  python test scripting, data handling and reporting\nLaboratory experience
 , including hands-on use of equipment: oscilloscope, logic analyzer, etc.\
 nExcellent problem-solving skills, good communication skills and ability t
 o work cooperatively in a team environment\nDebug issues with SOC IP and b
 oards as needed.\n\nAttributes of a Groqster:\nHumility - Egos are checked
  at the door\nCollaborative & Team Savvy - We make up the smartest person 
 in the room, together\nGrowth & Giver Mindset - Learn it all versus know i
 t all, we share knowledge generously\nCurious & Innovative - Take a creati
 ve approach to projects, problems, and design\nPassion, Grit, & Boldness -
  no limit thinking, fueling informed risk taking\n\nRegistration Category:
  Technical Program Reg Pass, Workshop Reg Pass, Tutorial Reg Pass, Exhibit
 s Reg Pass\n\nCompany: Groq\n\nIn-Person / Remote: In-person\n\nPart Time 
 / Full Time: Full Time\n\nPosition Type: Permanent\n\n
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