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DTSTAMP:20260202T201224Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T165600
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UID:submissions.supercomputing.org_SC25_sess553_job301@linklings.com
SUMMARY:Staff DFT Engineer
DESCRIPTION:Mission:\nAs a Staff DFT Engineer, you will be responsible to 
 enable Groq’s next‑generation LPU by designing, integrating, and validatin
 g cutting‑edge DFT solutions.\n\nResponsibilities & opportunities in this 
 role:\nBuild & Own End‑to‑End DFT Flow: Design a production‑ready DFT flow
  from scratch, select tools from an industry‑leading EDA partner , create 
 reusable templates, scripts, and best‑practice guidelines.\nRTL DFT DRC & 
 Optimization: Run DFT DRC on RTL blocks, propose fixes, and deliver RTL th
 at meets timing, area, and power targets.\nTiming Closure & Sign‑off: Writ
 e DFT‑specific timing constraints, work with physical design to close timi
 ng in test mode, and sign off test‑mode constraints.\nTest Vector Developm
 ent: Generate ATPG, IJTAG, and MBIST vectors; run RTL and gate‑level simul
 ations to achieve high coverage and verify functional path exercise.\nPost
 ‑Silicon Bring‑up: Partner with silicon validation teams to run patterns o
 n silicon, troubleshoot ATE issues, and streamline validation cycles.\nAut
 omation & Workflow Improvement: Identify bottlenecks, develop Tcl/Python a
 utomation, and integrate new tools to reduce manual effort and boost produ
 ctivity.\nDocumentation & Knowledge Transfer: Maintain version‑controlled 
 DFT documentation, create a “DFT playbook,” and lead knowledge‑sharing ses
 sions.\n\nIdeal candidates have/are:\nBachelor's or Master's degree in Ele
 ctrical Engineering or Computer Engineering. \n8+ years of industry experi
 ence with Design for Test (DFT) for high-performance ASICs.\nProven hands‑
 on experience with industry‑leading DFT tools, techniques and methodologie
 s for large SOC/ASIC designs. \nExpert in core DFT techniques: ATPG, scan 
 compression, MBIST, IJTAG, IEEE -1500, Logic BIST, test‑pattern translatio
 n, and yield learning.\nExperience with UDFM’s such as Cell Aware and Smal
 l Delay Defect.\nExperience in ATPG Streaming SCAN Network (SSN) implement
 ation. \nStrong timing‑analysis, constraint sign‑off, and gate‑level simul
 ation skills; adept at debugging DFT patterns on real silicon and ATE.\nSt
 rong knowledge of RTL to GDS methodologies and formal equivalence. \nExcel
 lent coding skills in Tcl and Python.\nStrong interpersonal and organizati
 onal skills.\nAbility and desire to work effectively as part of a team.\n\
 nAttributes of a Groqster:\nHumility - Egos are checked at the door\nColla
 borative & Team Savvy - We make up the smartest person in the room, togeth
 er\nGrowth & Giver Mindset - Learn it all versus know it all, we share kno
 wledge generously\nCurious & Innovative - Take a creative approach to proj
 ects, problems, and design\nPassion, Grit, & Boldness - no limit thinking,
  fueling informed risk taking\n\nRegistration Category: Technical Program 
 Reg Pass, Workshop Reg Pass, Tutorial Reg Pass, Exhibits Reg Pass\n\nCompa
 ny: Groq\n\nIn-Person / Remote: Remote\n\nPart Time / Full Time: Full Time
 \n\nPosition Type: Permanent\n\n
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