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PRODID:Linklings LLC
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DTSTAMP:20260202T201224Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T165600
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UID:submissions.supercomputing.org_SC25_sess553_job300@linklings.com
SUMMARY:Senior Staff HW EDA Infrastructure/Methodology Engineer
DESCRIPTION:Mission: \nWe are seeking an experienced engineer to drive the
  next-generation infrastructure, methodology, and automation that will acc
 elerate our ASIC design cycle. In this role, you will establish best-in-cl
 ass flows, apply advanced AI/ML techniques to complex design and sign-off 
 challenges, and develop robust tooling that reduces time-to-tapeout while 
 enhancing quality of results (QoR).\n\nResponsibilities & opportunities in
  this role:\nOwn ASIC methodology end-to-end: Define and evolve Architectu
 ral Modeling → RTL → Design Verification → gates → P&R → sign-off flows.\n
 Lead AI-driven methodology across the full ASIC lifecycle: Define the stra
 tegy, roadmap, and guardrails for applying AI/ML from architectural invest
 igation through post-silicon, with measurable positive impacts on schedule
 , cost, and QoR.\nAutomate for speed and reproducibility: Build robust pip
 elines for build/test/run, artifact tracking, and results triage; make one
 -click “from RTL to sign-off” flows standard.\nScale compute and data: Des
 ign farm orchestration for thousands of concurrent jobs, manage license us
 age, cache, and distributed storage for large design datasets.\nMake resul
 ts visible: Create dashboards and alerts for QoR trends, regressions, and 
 SLA adherence; enable data-driven design decisions.\nPartner across teams:
  Collaborate with RTL, DV, PD, DFT, verification, and CAD to land new meth
 ods, support tapeout, and drive continuous improvement.\nCollaborate with 
 software engineering to elevate hardware methodology: Partner with platfor
 m, SRE, and tooling teams to apply software best practices for robust, sca
 lable, and developer-friendly ASIC design workflows.\n\nIdeal candidates h
 ave/are:\n7+ years building and maintaining ASIC flows in production (from
  RTL through sign-off) with proven tapeout experience.\nDeep knowledge of 
 at least two EDA domains: simulation, hardware emulation, logic synthesis,
  P&R, STA, formal/equiv, CDC/RDC, DFT/ATPG, physical verification, or powe
 r sign-off.\nStrong coding skills in Python and one of Tcl/C++; rigorous s
 oftware practices (version control, code review, testing).\nExperience bui
 lding CI/CD style automation for hardware (e.g., Jenkins/GitHub Actions, B
 uildKite, Bazel, containers).\nComfortable with Linux at scale and job sch
 edulers (e.g., LSF/Slurm/Kubernetes).\nAbility to translate engineer pain 
 points into reliable tools with excellent UX and documentation.\n\nPreferr
 ed qualifications\nHands-on experience with Synopsys (VCS/Verdi), Cadence 
 (Genus/Innovus/Tempus/Jasper) EDA tools.\nPractical ML experience (PyTorch
 /JAX/scikit-learn) and MLOps basics (feature/log pipelines, experiment tra
 cking).\nData engineering for EDA: metrics schemas, results warehousing (P
 ostgreSQL/BigQuery), dashboarding (Grafana), and anomaly detection.\nCloud
  HPC (AWS/GCP/Azure) for bursty EDA workloads; cost and license optimizati
 on.\nPower intent and low-power methodology (UPF/CPF), multi-corner multi-
 mode closure experience.\nPrior success introducing new methodology across
  multiple projects/teams.\n\nAttributes of a Groqster:\nHumility - Egos ar
 e checked at the door\nCollaborative & Team Savvy - We make up the smartes
 t person in the room, together\nGrowth & Giver Mindset - Learn it all vers
 us know it all, we share knowledge generously\nCurious & Innovative - Take
  a creative approach to projects, problems, and design\nPassion, Grit, & B
 oldness - no limit thinking, fueling informed risk taking\n\nRegistration 
 Category: Technical Program Reg Pass, Workshop Reg Pass, Tutorial Reg Pass
 , Exhibits Reg Pass\n\nCompany: Groq\n\nIn-Person / Remote: Remote\n\nPart
  Time / Full Time: Full Time\n\nPosition Type: Permanent\n\n
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