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DTSTAMP:20260202T201224Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T165500
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UID:submissions.supercomputing.org_SC25_sess553_job299@linklings.com
SUMMARY:Senior Staff Formal Verification Engineer
DESCRIPTION:Mission: \nThis position will focus on formal verification of 
 Groq’s next generation hardware. Through this work term, the successful ca
 ndidate will work alongside experienced engineers to help verify complex d
 igital designs using formal verification techniques and tools. You will be
  involved in tasks ranging from setting up formal verification environment
 s, running automated checks, debugging formal proofs, and supporting the i
 ntegration of formal verification tools into the overall verification flow
 .\n\nResponsibilities & opportunities in this role:\nVerify hardware featu
 res of Language Process Unit (LPU).\nCross-functional Collaboration: Partn
 er with architecture/RTL teams to specify properties, resolve deep design 
 issues, and influence micro-architecture decisions.\nFormal verification e
 xecution: \nLeverage and unleash the power of formal verification to rigor
 ously verify critical design properties and ensure compliance with specifi
 cations, as well as minimize spec ambiguities.\nDebug findings and collabo
 rate with stakeholders in an efficient manner.\nSupport silicon bring-up a
 nd debug using formal methods where it applies.\nMethodology Leadership: D
 evelop and implement advanced formal verification environments and methodo
 logies for complex ASIC designs, including automated flows for scalability
  and efficiency.\nMentorship: Train and coach junior engineers on formal t
 echniques and best practices; Help on methodology/FAQ documentation.\nInno
 vate. Contribute to developing future verification strategies for validati
 ng future accelerator chips and hardware architectures for ML workloads. \
 n\nIdeal candidates have/are:\nBS degree in electrical engineering, or rel
 ated fields, or equivalent practical experience; advance degrees (MS or Ph
 D) is a plus\n8+ years in ASIC verification with 5+ years focused on forma
 l verification methods\nMastery of SystemVerilog Assertions (SVA) and form
 al property verification\nProficient on at least one popular formal verifi
 cation tools in the industry(JapserGold, VC Formal, etc.)\nStrong analytic
 al skills and attention to detail when debugging complex issues\nGood scri
 pting skills for flow automation(tcl, python, etc.)\nGood written and oral
  communication skills\nMust be authorized to work in the United States or 
 Canada\nProven success in full-cycle formal sign-off for complex compute b
 locks\nExpertise in formal apps: sequential equivalence checks, datapath, 
 connectivity, etc.\nDeep understanding of LPU or GPU architecture/design\n
 \nAttributes of a Groqster:\nHumility - Egos are checked at the door\nColl
 aborative & Team Savvy - We make up the smartest person in the room, toget
 her\nGrowth & Giver Mindset - Learn it all versus know it all, we share kn
 owledge generously\nCurious & Innovative - Take a creative approach to pro
 jects, problems, and design\nPassion, Grit, & Boldness - no limit thinking
 , fueling informed risk taking\n\nRegistration Category: Technical Program
  Reg Pass, Workshop Reg Pass, Tutorial Reg Pass, Exhibits Reg Pass\n\nComp
 any: Groq\n\nIn-Person / Remote: Remote\n\nPart Time / Full Time: Full Tim
 e\n\nPosition Type: Permanent\n\n
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