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DTSTAMP:20260202T201224Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T165500
DTEND;TZID=America/Chicago:20251117T165500
UID:submissions.supercomputing.org_SC25_sess553_job298@linklings.com
SUMMARY:Senior Technology Manager
DESCRIPTION:Arm’s Central Technology (CT) organization is seeking a Techno
 logy Manager to lead requirements and roadmap development for Arm’s infras
 tructure subsystem IP — including interconnect (CMN, NoC), memory products
 , control (GIC, MMU), and debug, Embedded Logic Analyzer, Coresight) techn
 ologies.\n\nWhile the initial emphasis is on server and networking Infrast
 ructure, this role spans multiple business lines — ensuring that the subsy
 stem technologies defined within CT are reusable and driven across Automot
 ive, IoT/EdgeAI, and Client applications.\n\nYou will work closely with en
 gineering, architecture, product, and partner teams to translate market ne
 eds into technical direction, maintain subsystem roadmaps, and validate th
 em through engagement with internal and external partners.\n\nResponsibili
 ties:\nDevelop and maintain technical requirements and multi-year technolo
 gy roadmaps for interconnect, memory, and system IP components!\nDefine lo
 ng-term evolution plans for Arm’s next-generation interconnect, ensuring a
 lignment with Infrastructure and cross-market needs.\nPartner with Product
  Management and Business Lines to align subsystem technology development w
 ith solution-level roadmaps.\nCollaborate with IP and implementation engin
 eering teams to ensure technology definitions are practical and implementa
 tion-ready for partner use.\nEngage with customers and ecosystem partners 
 to validate roadmap assumptions and collect technical feedback.\nIdentify 
 market and competitive trends that inform the direction of interconnect an
 d system IP evolution.\nCoordinate with program and technical leads to ali
 gn dependencies, schedules, and breakthroughs across CE, CT, SE, and busin
 ess lines.\nChip in to technology planning processes and improvements acro
 ss the Technology Management function.\nRequired Skills and Experience :\n
 Shown experience in interconnect, memory, or SoC subsystem design and inte
 gration.\nStrong understanding of system IP (Coherent Mesh fabric, NoC, MM
 U, GIC, memory controllers, PCIe, Debug). Understanding of SoC boot flow, 
 D2D, security.\nExperience developing or supporting SoC-level design and i
 ntegration flows.\nValidated ability to define requirements and lead techn
 ical trade-offs across IPs.\nClear and concise communicator able to interf
 ace effectively with architects and engineering teams.\n“Nice To Have” Ski
 lls and Experience :\nExperience developing or maintaining roadmaps for in
 terconnect or memory subsystem IP.\nKnowledge of coherency protocols, LPDD
 R, and on-chip fabric standards.\nFamiliarity with performance analysis or
  verification methodologies for large subsystems.\nCross-domain experience
  applying server/networking tech to Automotive or EdgeAI systems.\nIn Retu
 rn:\nYou will develop the roadmap for Arm’s core interconnect and control 
 subsystems, ensuring they are strategically aligned and technically valida
 ted across markets. While the initial focus is infrastructure, you will wo
 rk across line of business and customers to ensure these foundational tech
 nologies are robust, driven, and reusable across Arm’s diverse product por
 tfolio. Your ownership of requirement specs and roadmap rigor will ensure 
 subsystem coherence across product generations — enabling Arm to scale fro
 m IP to complete system solutions.\n\n Our 10x mindset guides how we engin
 eer, collaborate, and grow. Understand what it means and how to reflect 10
 x in your work:https://careers.arm.com/en/10x-mindset\n\nRegistration Cate
 gory: Technical Program Reg Pass, Workshop Reg Pass, Tutorial Reg Pass, Ex
 hibits Reg Pass\n\nCountry: United States of America\n\nCompany: ARM\n\nIn
 -Person / Remote: In-person\n\nPart Time / Full Time: Full Time\n\nPositio
 n Type: Permanent\n\n
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