BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260202T201222Z
LOCATION:Hall 6
DTSTART;TZID=America/Chicago:20251117T163400
DTEND;TZID=America/Chicago:20251117T163400
UID:submissions.supercomputing.org_SC25_sess553_job224@linklings.com
SUMMARY:Ethernet ASIC Design Engineer
DESCRIPTION:Cornelis Networks is hiring talented Sr. ASIC Design Engineers
  with deep experience in one or more of the key areas required to build th
 e world-class SoCs to be deployed in high performance computing, high perf
 ormance data analytics, and artificial intelligence interconnect solutions
 . A good candidate will have 15+ years of ASIC design experience, with 10+
  years of relevant experience in networking hardware design, proven expert
 ise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSe
 c. and their application in high-speed data processing/networking.\n\nKey 
 Responsibilities:\n- Design and implement advanced Ethernet protocols for 
 next-generation Ethernet switch ASICs, focusing on RTL development.\n- Dev
 elop microarchitecture specifications for Ethernet protocol blocks.\n- Imp
 lement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2,
  VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines us
 ing Verilog/System Verilog.\n- Collaborate with verification engineers to 
 create block- and system-level test plans to ensure comprehensive design c
 overage.\n- Define timing constraints for RTL blocks and work with Physica
 l Design engineers to optimize timing closure.\n- Support post-silicon val
 idation, collaborating with hardware, firmware, and software teams to debu
 g and resolve ASIC issues.\n- Contribute to performance optimization and p
 ower-aware design strategies for Ethernet subsystems.\n\nMinimum Qualifica
 tions:\nB.S. or M.S. degree in Computer Engineering, Electrical Engineerin
 g, or related field.\n10+ years of industry experience in digital design w
 ith proficiency in Verilog and System Verilog.\nExperience in RTL design f
 or Ethernet protocols relevant to adapters and switches.\nFamiliarity with
  timing closure and modern physical design methodologies.\nProven ability 
 in system-level debug and root cause analysis of technical issues.\nStrong
  verbal and written communication skills.\n\nPreferred Qualifications:\nDe
 ep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 l
 ayers).\nPrior experience with Ethernet MAC integration and development of
  L2/L3/L4 protocols for ASICs, including system debug.\nExpertise in multi
 ple clock domain designs and asynchronous interfaces.\n10+ years of experi
 ence with scripting languages such as TCL, Python, or Perl.\nFamiliarity w
 ith EDA tools like Design Compiler, Spyglass, or PrimeTime.\n\nLocation: T
 his is a remote position for employees residing within the United States.\
 n\nWe offer a competitive compensation package that includes equity, cash,
  and incentives, along with health and retirement benefits. Our dynamic, f
 lexible work environment provides the opportunity to collaborate with some
  of the most influential names in the semiconductor industry.  \n\nAt Corn
 elis Networks your base salary is only one component of your comprehensive
  total rewards package. Your base pay will be determined by factors such a
 s your skills, qualifications, experience, and location relative to the hi
 ring range for the position. Depending on your role, you may also be eligi
 ble for performance-based incentives, including an annual bonus or sales i
 ncentives. \n\nIn addition to your base pay, you’ll have access to a broad
  range of benefits, including medical, dental, and vision coverage, as wel
 l as disability and life insurance, a dependent care flexible spending acc
 ount, accidental injury insurance, and pet insurance. We also offer genero
 us paid holidays, 401(k) with company match, and Open Time Off (OTO) for r
 egular full-time exempt employees. Other paid time off benefits include si
 ck time, bonding leave, and pregnancy disability leave. \n\nCornelis Netwo
 rks does not accept unsolicited resumes from headhunters, recruitment agen
 cies, or fee-based recruitment services. Cornelis Networks is an equal opp
 ortunity employer, and all qualified applicants will receive consideration
  for employment without regard to race, color, religion, sex, sexual orien
 tation, gender identity or expression, pregnancy, age, national origin, di
 sability status, genetic information, protected veteran status, or any oth
 er characteristic protected by law. We encourage applications from all qua
 lified candidates and will accommodate applicants’ needs under the respect
 ive laws throughout all stages of the recruitment and selection process.\n
 \nRegistration Category: Technical Program Reg Pass, Workshop Reg Pass, Tu
 torial Reg Pass, Exhibits Reg Pass\n\nCountry: United States of America\n\
 nCompany: Cornelis Networks\n\nIn-Person / Remote: Remote\n\nPart Time / F
 ull Time: Full Time\n\nPosition Type: Permanent\n\n
END:VEVENT
END:VCALENDAR
