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DTSTART;TZID=America/Chicago:20251117T122000
DTEND;TZID=America/Chicago:20251117T123000
UID:submissions.supercomputing.org_SC25_sess236_ws_risc110@linklings.com
SUMMARY:Bridging Simulation and Silicon: A Study of RISC-V Hardware and Fi
 reSim Simulation
DESCRIPTION:Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim M
 oraru, Jered Dominguez-Trujillo, Howard Pritchard, and Nandakishore Santhi
  (Los Alamos National Laboratory (LANL)); Farzad Fatollahi-Fard (Lawrence 
 Berkeley National Laboratory (LBNL)); and Galen Shipman (Los Alamos Nation
 al Laboratory (LANL))\n\nRISC-V ISA-based processors have emerged as power
 ful, energy-efficient computing platforms, with the Milk-V Pioneer marking
  the first desktop-grade RISC-V system. Growing interest from academia and
  industry highlights their potential in high-performance computing (HPC). 
 The open-source, FPGA-accelerated FireSim framework enables flexible archi
 tectural exploration using RISC-V cores, but systematic evaluation of its 
 accuracy against real hardware remains limited.\n\nThis study models a com
 mercially available single-board computer and a desktop-grade RISC-V CPU i
 n FireSim. Benchmarks under single-core and four-core configurations were 
 used to align simulation parameters with hardware behavior. Using the best
 -matching configuration, performance was assessed with a representative mi
 ni-application and the LAMMPS molecular dynamics code.\n\nResults show tha
 t FireSim offers useful insights into architectural performance trends, bu
 t runtime discrepancies persist due to simulation limitations and incomple
 te CPU performance specifications, which constrain precise configuration m
 atching.\n\nRecording: Livestreamed, Recorded\n\nRegistration Category: Te
 chnical Program Reg Pass, Workshop Reg Pass\n\nSession Chairs: Nick Brown 
 (Edinburgh Parallel Computing Centre (EPCC); University of Edinburgh, Scot
 land); David Donofrio (Tactical Computing Laboratories LLC, Lawrence Berke
 ley National Laboratory (LBNL)); Teresa Cervero (Barcelona Supercomputing 
 Center (BSC)); Daniele Gregori (E4 Computer Engineering); and Matthew Turn
 er (Hewlett Packard Enterprise (HPE))\n\n
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