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DTSTART;TZID=America/Chicago:20251117T094000
DTEND;TZID=America/Chicago:20251117T095000
UID:submissions.supercomputing.org_SC25_sess236_ws_risc108@linklings.com
SUMMARY:Simulating Hybrid Analog + RISC-V Systems for HPC Applications
DESCRIPTION:Cameron Durbin (University of Oregon), Jacob Flores (Sandia Na
 tional Laboratories), Thomas Weatherly (Georgia Tech Research Institute), 
 and Ben Feinberg (Sandia National Laboratories)\n\nAs digital scaling tren
 ds have slowed over the past decade, there has been renewed interest in ne
 w computing paradigms such as analog. Analog computing has the potential t
 o provide performance and efficiency beyond what is achievable by digital 
 systems; however, many challenges remain. One such challenge is supporting
  complex applications using analog components that implement few computati
 onal kernels. We consider on a class of hybrid analog + digital systems wh
 ere analog accelerators are used as tightly integrated coprocessors within
  each core. The RISC-V ISA simplifies the design of hybrid systems, provid
 ing a mature software stack for the digital components allowing system des
 igners to focus on the analog-specific aspects of the architecture and sof
 tware. To investigate the viability of these architectures for high perfor
 mance computing we evaluate two iterative linear solvers using hybrid anal
 og + RISC-V processors using the Structural Simulation Toolkit.\n\nRecordi
 ng: Livestreamed, Recorded\n\nRegistration Category: Technical Program Reg
  Pass, Workshop Reg Pass\n\nSession Chairs: Nick Brown (Edinburgh Parallel
  Computing Centre (EPCC); University of Edinburgh, Scotland); David Donofr
 io (Tactical Computing Laboratories LLC, Lawrence Berkeley National Labora
 tory (LBNL)); Teresa Cervero (Barcelona Supercomputing Center (BSC)); Dani
 ele Gregori (E4 Computer Engineering); and Matthew Turner (Hewlett Packard
  Enterprise (HPE))\n\n
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