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X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
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UID:submissions.supercomputing.org_SC25_sess236_ws_risc106@linklings.com
SUMMARY:A RISC-V Vector Extension for Multi-word Arithmetic
DESCRIPTION:Yunhao Lan, Larry Tang, Naifeng Zhang, Youngjin Eum, James Hoe
 , and Franz Franchetti (Carnegie Mellon University)\n\nMulti-word arithmet
 ic plays a critical role in high-performance computing (HPC) as it enables
  arithmetic on operands exceeding a processor’s native word size. For exam
 ple, many cryptographic kernels, such as number theoretic transform, rely 
 on multi-word arithmetic to compute log₂(𝑞)-bit integer arithmetic, accele
 rating mod-𝑞 polynomial multiplication in post-quantum cryptography. To mi
 tigate carry-propagation bottlenecks in multi-word arithmetic, prior work 
 proposed code-generation approaches targeting GPUs and domain-specific acc
 elerators (DSAs) with native large-integer support. However, GPU-based app
 roaches tend to be less energy-efficient, while DSA designs incur non-triv
 ial non-recurring engineering. Therefore, our work evaluates the potential
  for RISC-V in HPC and explores multi-word arithmetic using RISC-V. We pro
 pose a general modeling-based multi-word extension on the RISC-V Vector (R
 VV) ISA. Furthermore, we develop comprehensive performance models to analy
 ze performance consistency across host vector processing systems with dive
 rse microarchitectural configurations. Our work demonstrates that targeted
  architectural extensions can further saturate the pipeline by enhancing R
 VV’s carry-propagation support.\n\nRecording: Livestreamed, Recorded\n\nRe
 gistration Category: Technical Program Reg Pass, Workshop Reg Pass\n\nSess
 ion Chairs: Nick Brown (Edinburgh Parallel Computing Centre (EPCC); Univer
 sity of Edinburgh, Scotland); David Donofrio (Tactical Computing Laborator
 ies LLC, Lawrence Berkeley National Laboratory (LBNL)); Teresa Cervero (Ba
 rcelona Supercomputing Center (BSC)); Daniele Gregori (E4 Computer Enginee
 ring); and Matthew Turner (Hewlett Packard Enterprise (HPE))\n\n
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