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DTSTART;TZID=America/Chicago:20251117T090000
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UID:submissions.supercomputing.org_SC25_sess236_misc193@linklings.com
SUMMARY:Invited talk: Cuzco from Open-source to a High Performance Computi
 ng CPU Design
DESCRIPTION:Shashank Nemawarkar\n\nThe RISC-V ISA, with the RVA23 compatib
 ility profile, is enabling innovation to meet the power-performance-area (
 PPA) needs of the most demanding computing workloads. Condor Computing pre
 sents Cuzco, a novel RISC-V processor IP design, for inclusion in customer
  System-on-Chips (SoCs) which will compete with current top-of-the-line pr
 ocessors in high-end data center and high-performance computing (HPC) appl
 ications, while delivering better PPA results. This paper describes how Cu
 zco’s design demonstrates that a rapidly maturing RISC-V ecosystem provide
 s the Instruction Set Architecture (ISA), tools and platforms which, when 
 enhanced with internal efforts, can achieve high PPA efficiencies without 
 sacrificing performance. Cuzco is a new class of processor design built ar
 ound a novel compiler-like instruction scheduling for runtime execution to
  enable high performance while optimizing power and area dimensions throug
 h dynamic and physical scaling, including dynamic and/or physical %optimiz
 ation of resources for dispatch and retire width. Basline 8-way design ach
 ieves a performance of 15-20 SpecInt2K6/GHz.\n\nRecording: Livestreamed, R
 ecorded\n\nRegistration Category: Technical Program Reg Pass, Workshop Reg
  Pass\n\nSession Chairs: Nick Brown (Edinburgh Parallel Computing Centre (
 EPCC); University of Edinburgh, Scotland); David Donofrio (Tactical Comput
 ing Laboratories LLC, Lawrence Berkeley National Laboratory (LBNL)); Teres
 a Cervero (Barcelona Supercomputing Center (BSC)); Daniele Gregori (E4 Com
 puter Engineering); and Matthew Turner (Hewlett Packard Enterprise (HPE))\
 n\n
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