BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Chicago X-LIC-LOCATION:America/Chicago BEGIN:DAYLIGHT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 TZNAME:CDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260202T201316Z LOCATION:242 DTSTART;TZID=America/Chicago:20251117T090000 DTEND;TZID=America/Chicago:20251117T123000 UID:submissions.supercomputing.org_SC25_sess236@linklings.com SUMMARY:International Workshop on RISC-V for HPC (RISCVHPC) DESCRIPTION:RISC-V is an open standard instruction set architecture (ISA) which enables the open development of CPUs and a shared common software ec osystem. There are already over 15 billion RISC-V cores, which are acceler ating rapidly. Nonetheless, for all the successes that RISC-V has faced, i t is yet to become popular in HPC. Recent advances, however, such as data center RISC-V-based CPUs and PCIe accelerators, mean that this technology is becoming a more realistic proposition for our workloads. This workshop aims to connect those currently involved in RISC-V with the wider HPC comm unity. We look to bring together RISC-V experts with scientific software d evelopers, vendors, and supercomputing center operators to explore the adv antages, challenges, and opportunities that RISC-V can bring to HPC. Furth ermore, we aim to further expand the RISC-V HPC SIG, enabling interested a ttendees to participate in one of the most exciting open-source technologi cal activities of our time.\n\nAssessing a RISC-V Accelerator for Cross-Se ction Lookup in Chipyard\n\nHigh-fidelity nuclear reactor simulations usin g Monte Carlo\nneutron transport face bottlenecks in neutron cross-section \nlookups. We designed a custom RISC-V accelerator for\nRSBench, integrate d with a RocketCore in Chipyard. The\npipelined design employs Humlíček’s 8th-order rational ap-\npr...\n\n\nAndrew Ledbetter, Kazutomo Yoshii, and John Tramm (Argonne National Laboratory (ANL))\n---------------------\nIzh iRISC-V - a RISC-V-based Processor with Custom ISA Extension for Spiking N euron Networks Processing with Izhikevich Neurons\n\nSpiking Neural Networ k processing promises to provide high energy efficiency due to the sparsit y of the spiking events. However, when realized on general-purpose hardwar e -- such as a RISC-V processor -- this promise can be undermined and over shadowed by the inefficient code, stemming from repeated ...\n\n\nWiktor J an Szczerek and Artur Podobas (KTH Royal Institute of Technology)\n------- --------------\nMorning Break - International Workshop on RISC-V for HPC ( RISCVHPC)\n---------------------\nInvited talk: Cuzco from Open-source to a High Performance Computing CPU Design\n\nThe RISC-V ISA, with the RVA23 compatibility profile, is enabling innovation to meet the power-performanc e-area (PPA) needs of the most demanding computing workloads. Condor Compu ting presents Cuzco, a novel RISC-V processor IP design, for inclusion in customer System-on-Chips (SoCs) which will comp...\n\n\nShashank Nemawarka r\n---------------------\nEnabling the syscall_intercept library for RISC- V\n\nPetar Andrić, Ramon Nou, Aaron Call, and Guillem Senabre (Barcelona S upercomputing Center (BSC))\n---------------------\nIs RISC-V ready for Hi gh Performance Computing? An evaluation of the Sophon SG2044\n\nThe pace o f RISC-V adoption continues to grow rapidly, yet for the successes enjoyed in areas such as embedded computing, RISC-V is yet to gain ubiquity in Hi gh Performance Computing (HPC). The Sophon SG2044 is SOPHGO's next generat ion 64-core high performance CPU that has been designed for workstat...\n\ n\nNick Brown (Edinburgh Parallel Computing Centre (EPCC); University of E dinburgh, Scotland)\n---------------------\nDyninst on the RISC-V: Binary Instrumentation in Support of Performance, Debugging, and Other Tools\n\nB inary instrumentation provides the ability to instrument and modify a prog ram after the compilation process has completed. Operating on the binary l evel allows instrumentation of the program as it was produced by the compi ler. In addition, it can operate on programs or libraries for which you ma y n...\n\n\nCheng-Hsun Angus He, Ronak Chauhan, James A. Kupsch, Hsuan-Hen g Wu, and Barton P. Miller (University of Wisconsin-Madison)\n------------ ---------\nA RISC-V Vector Extension for Multi-word Arithmetic\n\nMulti-wo rd arithmetic plays a critical role in high-performance computing (HPC) as it enables arithmetic on operands exceeding a processor’s native word siz e. For example, many cryptographic kernels, such as number theoretic trans form, rely on multi-word arithmetic to compute log₂(ү...\n\n\nYunhao Lan, Larry Tang, Naifeng Zhang, Youngjin Eum, James Hoe, and Franz Franche tti (Carnegie Mellon University)\n---------------------\nRISC-V Vectorizat ion Coverage for HPC: A TSVC-Based Analysis\n\nThe RISC-V Vector Extension (RVV) introduces scalable, vector-length–agnostic operations with strong potential for high-performance computing (HPC). This paper presents a TSVC -based instruction coverage analysis of RVV to evaluate current compiler a uto-vectorization support. We compile TSVC wi...\n\n\nHung-Ming Lai (Natio nal Tsing Hua University, Taiwan; Lawrence Livermore National Laboratory ( LLNL)); Pei-Hung Lin (Lawrence Livermore National Laboratory (LLNL)); Maya Gokhale (Lawrence Livermore National Laboratory); Ivy Peng (KTH Royal Ins titute of Technology); Hiren Patel (University of Waterloo); and Jenq-Kuen Lee (National Tsing Hua University)\n---------------------\nAccelerating Gravitational N-Body Simulations Using the RISC-V-Based Tenstorrent Wormho le\n\nAlthough originally developed primarily for artificial intelligence workloads, RISC-V-based accelerators are also emerging as attractive platf orms for high-performance scientific computing. In this work, we present o ur approach to accelerating an astrophysical N-body code on the RISC-V-bas ed Wormhol...\n\n\nJenny Lynn Almerol and Elisabetta Boella (E4 Computer E ngineering), Mario Spera (Scuola Internazionale Superiore di Studi Avanzat i (SISSA)), and Daniele Gregori (E4 Computer Engineering)\n--------------- ------\nBridging Simulation and Silicon: A Study of RISC-V Hardware and Fi reSim Simulation\n\nRISC-V ISA-based processors have emerged as powerful, energy-efficient computing platforms, with the Milk-V Pioneer marking the first desktop-grade RISC-V system. Growing interest from academia and indu stry highlights their potential in high-performance computing (HPC). The o pen-source, FPGA-acceler...\n\n\nAtanu Barai, Kamalavasan Kamalakkannan, P atrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, an d Nandakishore Santhi (Los Alamos National Laboratory (LANL)); Farzad Fato llahi-Fard (Lawrence Berkeley National Laboratory (LBNL)); and Galen Shipm an (Los Alamos National Laboratory (LANL))\n---------------------\nSimulat ing Hybrid Analog + RISC-V Systems for HPC Applications\n\nAs digital scal ing trends have slowed over the past decade, there has been renewed intere st in new computing paradigms such as analog. Analog computing has the pot ential to provide performance and efficiency beyond what is achievable by digital systems; however, many challenges remain. One such chal...\n\n\nCa meron Durbin (University of Oregon), Jacob Flores (Sandia National Laborat ories), Thomas Weatherly (Georgia Tech Research Institute), and Ben Feinbe rg (Sandia National Laboratories)\n\nRecording: Livestreamed, Recorded\n\n Registration Category: Technical Program Reg Pass, Workshop Reg Pass\n\nSe ssion Chairs: Nick Brown (Edinburgh Parallel Computing Centre (EPCC); Univ ersity of Edinburgh, Scotland); David Donofrio (Tactical Computing Laborat ories LLC, Lawrence Berkeley National Laboratory (LBNL)); Teresa Cervero ( Barcelona Supercomputing Center (BSC)); Daniele Gregori (E4 Computer Engin eering); and Matthew Turner (Hewlett Packard Enterprise (HPE)) END:VEVENT END:VCALENDAR