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DTSTART;TZID=America/Chicago:20251117T103000
DTEND;TZID=America/Chicago:20251117T105500
UID:submissions.supercomputing.org_SC25_sess217_ws_drbsd101@linklings.com
SUMMARY:Design and Implementation of a Custom Hardware Accelerator for SZx
  Compression in Chipyard
DESCRIPTION:Connor Bohannon, Kazutomo Yohsii, Sheng Di, Franck Cappello, a
 nd Antonino Miceli (Argonne National Laboratory (ANL))\n\nAbstract—Data mo
 vement bottlenecks have become the dominant performance limiter in modern 
 computing systems. At the same time, scientific detectors generate overwhe
 lming data\nvolumes; X-ray detectors may soon produce terabytes per second
  and high-energy physics experiments demand bandwidth on the order of peta
 bytes per second. Streaming compression can reduce data movement overheads
 , hardware accelerators can further enhance data flow, and the exploration
  of system-level hardware compressors represents an untapped opportunity. 
 This paper presents a preliminary study on enabling hardware evaluation of
  streaming compressors. We designed and implemented a custom hardware acce
 lerator for scientific data compression using modern hardware description 
 languages, providing a complete end-toend hardware acceleration system for
  CPU-based platforms. Our prototype features a multi-stage state machine, 
 parallel element processing, and optimized data transfers, achieving 1.45×
  speedup\nover a software baseline with comparable quality, with 31% fewer
  cycles per element and 45% faster compression throughput.\n\nRecording: L
 ivestreamed, Recorded\n\nRegistration Category: Technical Program Reg Pass
 , Workshop Reg Pass\n\nSession Chairs: Sheng Di (Argonne National Laborato
 ry (ANL), University of Chicago); Ana Gainaru (Oak Ridge National Laborato
 ry (ORNL)); Kento Sato (RIKEN Center for Computational Science (R-CCS)); X
 in Liang (University of Kentucky); and Jieyang Chen (University of Oregon)
 \n\n
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