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DTSTART;TZID=America/Chicago:20251117T114500
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UID:submissions.supercomputing.org_SC25_sess198_ws_pmbss112@linklings.com
SUMMARY:Implications of Full-System Modeling for Superconducting Architect
 ures
DESCRIPTION:Kunal Pai, Mahyar Samani, Anusheel Nand, and Jason Lowe-Power 
 (University of California, Davis)\n\nAs Moore's Law slows, superconducting
  electronics offer ultra-low-power, high-speed computation potential. This
  paper presents the first full-system superconducting architecture modelin
 g in gem5, evaluating superconducting cores, caches, and interconnects und
 er realistic workloads. We extend gem5 with cryogenic semiconductor (4 GHz
 ) and superconducting (100 GHz) RISC-V cores and multi-level caches, evalu
 ating RISC-V benchmarks and SPEC CPU2006 applications. We also integrate S
 RNoC, a superconducting interconnect, with the NOVA graph accelerator.\n\n
 Results show superconducting cores and caches achieve up to 24x speedup fo
 r compute-intensive workloads, but memory-intensive applications are bottl
 enecked by room-temperature DRAM (1.2x improvement). High cache bandwidth 
 requirements (800 GB/s) present design challenges. SRNoC provides 35-73x e
 nergy efficiency gains for narrow data paths but 1246x slowdown for wide d
 ata communication. Therefore, superconducting technology suits domain-spec
 ific accelerators better than general-purpose computing, with performance 
 dependent on workload memory access patterns and data widths.\n\nRecording
 : Livestreamed, Recorded\n\nRegistration Category: Technical Program Reg P
 ass, Workshop Reg Pass\n\nSession Chairs: Steven A. Wright (University of 
 York, England); Simon Hammond (National Nuclear Security Administration (N
 NSA)); and Sascha Hunold (Technical University of Vienna)\n\n
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