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DTSTART;TZID=America/Chicago:20251117T121500
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UID:submissions.supercomputing.org_SC25_sess198_ws_pmbss104@linklings.com
SUMMARY:Experiences of Porting Structured and Unstructured Stencil Applica
 tions to FPGA using SYCL
DESCRIPTION:Zadok Storkey, Steven Wright, and Ian Gray (University of York
 , England)\n\nIn this paper we explore a stencil application written in SY
 CL on both CPU and FPGA architectures.\nWe prepare two versions of the app
 lication, using a structured grid and an unstructured grid, and then optim
 ise these implementations for CPU and FPGA architectures, with a focus on 
 maintaining portability between both.\nWe benchmark the application on an 
 AMD CPU and an Intel Stratix 10 FPGA, seeking to answer whether we can tar
 get FPGAs productively from a single-source code base.\nOur findings indic
 ate that for low arithmetic intensity kernels FPGA performance is lacking 
 compared to CPU performance, suggesting that FPGA architectures may be uns
 uitable for such kernels, or that significant platform-specific optimisati
 ons may be required to reduce the performance gap, at the expense of devel
 oper productivity.\n\nRecording: Livestreamed, Recorded\n\nRegistration Ca
 tegory: Technical Program Reg Pass, Workshop Reg Pass\n\nSession Chairs: S
 teven A. Wright (University of York, England); Simon Hammond (National Nuc
 lear Security Administration (NNSA)); and Sascha Hunold (Technical Univers
 ity of Vienna)\n\n
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