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UID:submissions.supercomputing.org_SC25_sess198_ws_pmbsf125@linklings.com
SUMMARY:Modelling Load Imbalance In Shared Memory Multicore Systems
DESCRIPTION:Johannes Langguth (Simula Research Laboratory, University of B
 ergen); James Trotter (Simula Research Laboratory); and Xing Cai (Universi
 ty of Oslo, Simula Research Laboratory)\n\nMemory bandwidth has become the
  primary limiting factor of performance in many modern HPC applications, a
 nd it poses a limit to scalability because the achievable memory\nbandwidt
 h only grows linearly with a small number of CPU cores. When the number of
  cores concurrently using the memory system exceeds a threshold, the aggre
 gate memory bandwidth quickly saturates.\n\nTo estimate the time usage of 
 a computation dominated by memory\ntraffic, the mainstream strategy is to 
 divide the expected total memory\ntraffic volume by the maximum memory ban
 dwidth. However, this\nimplicitly assumes homogeneous memory traffic which
  is often not the case, leading to inaccurate time estimates by\nthe mains
 tream strategy.\n\nIn this paper, we present a new performance model that 
 specifically\ntargets inhomogeneity in per-core memory traffic.\nThe new r
 equires only three hardware  parameters. Using several cases of uneven per
 -core memory traffic, we demonstrate its advantage\n over the mainstream s
 trategy.\n\nRecording: Livestreamed, Recorded\n\nRegistration Category: Te
 chnical Program Reg Pass, Workshop Reg Pass\n\nSession Chairs: Steven A. W
 right (University of York, England); Simon Hammond (National Nuclear Secur
 ity Administration (NNSA)); and Sascha Hunold (Technical University of Vie
 nna)\n\n
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