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DTSTART;TZID=America/Chicago:20251119T163700
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UID:submissions.supercomputing.org_SC25_sess170_pap417@linklings.com
SUMMARY:SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil
  Computations via Structured Sparsity Transformation
DESCRIPTION:Qi Li (University of Science and Technology of China); Kun Li 
 and Liang Yuan (Microsoft Corporation); Yunquan Zhang (University of Chine
 se Academy of Sciences, Beijing); Junshi Chen and Hong An (University of S
 cience and Technology of China); and Ting Cao and Mao Yang (Microsoft Corp
 oration)\n\nSparse Tensor Cores offer exceptional performance gains for AI
  workloads by exploiting structured 2:4 sparsity. However, their potential
  remains untapped for core scientific workloads such as stencil computatio
 ns, which exhibit irregular sparsity patterns.\n\nThis paper presents Spar
 Stencil, the first system to retarget sparse TCUs for scientific stencil c
 omputations through structured sparsity transformation. SparStencil introd
 uces three key techniques:\n\n(1) Adaptive Layout Morphing, which restruct
 ures stencil patterns into staircase-aligned sparse matrices via a flatten
 -and-crush pipeline;\n\n(2) Structured Sparsity Conversion, which formulat
 es transformation as a graph matching problem to ensure compatibility with
  2:4 sparsity constraints;\n\n(3) Automatic Kernel Generation, which compi
 les transformed stencils into optimized sparse MMA kernels via layout sear
 ch and table-driven memory mapping.\n\nEvaluated on 79 stencil kernels spa
 nning diverse scientific domains, SparStencil achieves up to 7.1x speedup 
 (3.1x on average) over state-of-the-art framework, while reducing code com
 plexity and matching or exceeding expert-tuned performance in both compute
  throughput and memory efficiency.\n\nTag: Algorithms, Best Student Paper 
 Finalist\n\nRecording: Livestreamed, Recorded\n\nRegistration Category: Te
 chnical Program Reg Pass\n\nSession Chair: Albert-Jan Yzelman (Huawei Tech
 nologies Switzerland AG)\n\n
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