Session

DescriptionRISC-V is an open standard instruction set architecture (ISA) which enables the open development of CPUs and a shared common software ecosystem. There are already over 15 billion RISC-V cores, which are accelerating rapidly. Nonetheless, for all the successes that RISC-V has faced, it is yet to become popular in HPC. Recent advances, however, such as data center RISC-V-based CPUs and PCIe accelerators, mean that this technology is becoming a more realistic proposition for our workloads. This workshop aims to connect those currently involved in RISC-V with the wider HPC community. We look to bring together RISC-V experts with scientific software developers, vendors, and supercomputing center operators to explore the advantages, challenges, and opportunities that RISC-V can bring to HPC. Furthermore, we aim to further expand the RISC-V HPC SIG, enabling interested attendees to participate in one of the most exciting open-source technological activities of our time.