Session
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4th International Workshop on Cyber Security in High Performance Computing (S-HPC)
Session Chairs
DescriptionThe goal of this workshop is to bring together researchers and practitioners in cybersecurity and HPC. Security in high performance computing (HPC) has traditionally been an “operational” challenge (i.e., restricting access and usage to certified users). Thus, despite significant advances in our understanding and mitigation of vulnerabilities, the cybersecurity research community has been somewhat disconnected from the HPC community. Recent increases in the heterogeneity of both the underlying platforms of HPC and the community of HPC-level users and applications point to an important and growing need for connection and synergy between these two communities.
Event Type
Workshop
TimeSunday, 16 November 20252:00pm - 5:30pm CST
Location242
Livestreamed
Recorded
TP
W
Presentations
| 2:00pm - 2:03pm CST | Opening Remarks Presenter | |
| 2:03pm - 2:22pm CST | Securing HDF5 Plugins with Digital Signatures | |
| 2:22pm - 2:41pm CST | CASSE: Targeted Threat Modeling for Data Management Libraries | |
| 2:41pm - 3:00pm CST | 60 Security Professionals Walk Into A Room: Outbrief from the 3rd HPC Security Technical Exchange Presenter | |
| 3:00pm - 3:30pm CST | Afternoon Break - Workshop on Cyber Security in High Performance Computing (S-HPC) | |
| 3:30pm - 4:15pm CST | Threads of Trouble: Unveiling GPU Software and Hardware Security Flaws Presenter | |
| 4:15pm - 4:35pm CST | Dynamic Factor Graphs for Attack Preemption | |
| 4:35pm - 4:55pm CST | Evaluating Trusted Execution Environment Performance for Genome Sequence Alignment: An AMD SEV Case Study | |
| 4:55pm - 5:25pm CST | Panel: NIST 800-234 : High-Performance Computing (HPC) Security Overlay Moderator | |
| 5:25pm - 5:30pm CST | Closing Remarks Presenter |
