Session
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6th Workshop on Heterogeneity and Memory Systems (HMEM)
Session Chairs
DescriptionHeterogeneity is ubiquitous, not only in terms of processing units but also memories and networks. As heterogeneity increases, memory subsystems play an even more important role to attain performance, from their technology to the system architecture to the software management and programming model. While CPU-only compute nodes are becoming rare instances, heterogeneous memory architectures have recently emerged and revolutionized the traditional memory hierarchy. Current and upcoming architectures may well comprise multiple memory technologies next to DRAM, accelerators with dedicated memories, or even specific expansion cards hosting memory alone, such as: 3D-stacked memory, high-bandwidth multi-channel RAM, unified/shared memory on accelerators, Compute Express Link (CXL)-based architectures, persistent memory, or MRDIMMs. The HMEM workshop already has a tradition of serving as a forum to bring together researchers from the HPC community to present and discuss ongoing research around the relationship between resource heterogeneity and memory systems.
Event Type
Workshop
TimeMonday, 17 November 20252:00pm - 5:30pm CST
Location240
Livestreamed
Recorded
TP
W
Presentations
| 2:00pm - 3:00pm CST | Featured Talk - ARMing GPUs: On the Memory Subsystem of Grace Hopper GH200 Presenter | |
| 3:00pm - 3:30pm CST | Afternoon Break - Sixth Workshop on Heterogeneity and Memory Systems (HMEM) | |
| 3:30pm - 3:54pm CST | Machine Learning-Guided Memory Optimization for DLRM Inference on Tiered Memory | |
| 3:54pm - 4:18pm CST | Performance Analysis of Compute Express Link (CXL) Memory Expansion with Data Interleaving | |
| 4:18pm - 4:42pm CST | A Limits Study of Memory-side Tiering Telemetry | |
| 4:42pm - 5:06pm CST | Summary: Hierarchical Framework for Multi-node Compute eXpress Link Memory Transactions | |
| 5:06pm - 5:30pm CST | Performance Characterization of CXL Memory and Its Use Cases |
