Presenter

Gabriel is a PhD student at EPCC, The University of Edinburgh. His work focuses on high-level dataflow abstractions for automatic generation of efficient hardware on FPGA, including designs with dynamic partial reconfiguration. During his PhD time he was an intern at HPE, were he developed Fortran HLS, a tool that integrates Fortran in the Vitis HLS ecosystem for the seamless generation of hardware from Fortran. More recently he interned at Pacific Northwest National Laboratory, where he worked on the development of an open-source dataflow architecture.