Presenter

Dr. Teresa Cervero García is a leading research engineer at Barcelona Supercomputing Center (BSC), working on the MareNostrum Experimental Exascale Platform (MEEP) project, which is a flexible FPGA-based emulation platform that explores hardware/software co-designs for exascale supercomputers and other hardware targets, based on European-developed IP. A major part of this has been to define, develop, and deploy an FPGA-based emulation platform targeting European-based exascale supercomputer RISC-V-based IP development, which Teresa is heavily involved in. She is also vice chair of the RISC-V HPC SIG. She earned her PhD in telecommunication engineering focused on hardware design, with experience in HDL languages and FPGA devices.