Presenter

Alexander Fell is a Senior Research Specialist at the University of Chicago, where he is part of the development of the DARPA-funded UpDown Project, a novel architecture for scalable graph processing. He has over 15 years of experience in high-performance computing, computer architecture, and compiler infrastructures, spanning academia and industry across the U.S., Europe, and Asia.

At Chicago, he designed and optimized the UpDown simulator, scaling from thousands to over 32 million compute nodes while achieving 500 billion instructions per second. He also developed a high-level compiler for UpDown, enabling domain scientists to map complex algorithms onto massively parallel hardware.

Previously, Alexander was a leading researcher at the Barcelona Supercomputing Center, where he advanced LLVM compiler optimizations for RISC-V vector processors and contributed to the European Processor Initiative. He also served as faculty in Singapore and India, focusing on embedded systems, security, and FPGA-based accelerators. His doctoral research at the Indian Institute of Science (IISc) explored reconfigurable dataflow multicore processors, supported by a DAAD fellowship.

He has co-authored numerous peer-reviewed publications in HPC, compiler design, and architecture, including the recent work presented here and now. He also holds patents in program protection and reconfigurable hardware.

Alexander’s research bridges system architecture and compiler design to push the boundaries of scalable, energy-efficient supercomputing.