Presentation
Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
DescriptionRISC-V ISA-based processors have emerged as powerful, energy-efficient computing platforms, with the Milk-V Pioneer marking the first desktop-grade RISC-V system. Growing interest from academia and industry highlights their potential in high-performance computing (HPC). The open-source, FPGA-accelerated FireSim framework enables flexible architectural exploration using RISC-V cores, but systematic evaluation of its accuracy against real hardware remains limited.
This study models a commercially available single-board computer and a desktop-grade RISC-V CPU in FireSim. Benchmarks under single-core and four-core configurations were used to align simulation parameters with hardware behavior. Using the best-matching configuration, performance was assessed with a representative mini-application and the LAMMPS molecular dynamics code.
Results show that FireSim offers useful insights into architectural performance trends, but runtime discrepancies persist due to simulation limitations and incomplete CPU performance specifications, which constrain precise configuration matching.
This study models a commercially available single-board computer and a desktop-grade RISC-V CPU in FireSim. Benchmarks under single-core and four-core configurations were used to align simulation parameters with hardware behavior. Using the best-matching configuration, performance was assessed with a representative mini-application and the LAMMPS molecular dynamics code.
Results show that FireSim offers useful insights into architectural performance trends, but runtime discrepancies persist due to simulation limitations and incomplete CPU performance specifications, which constrain precise configuration matching.
Author/Presenters
Event Type
Workshop
TimeMonday, 17 November 202512:20pm - 12:30pm CST
Location242