Presentation
A RISC-V Vector Extension for Multi-word Arithmetic
DescriptionMulti-word arithmetic plays a critical role in high-performance computing (HPC) as it enables arithmetic on operands exceeding a processor’s native word size. For example, many cryptographic kernels, such as number theoretic transform, rely on multi-word arithmetic to compute log₂(𝑞)-bit integer arithmetic, accelerating mod-𝑞 polynomial multiplication in post-quantum cryptography. To mitigate carry-propagation bottlenecks in multi-word arithmetic, prior work proposed code-generation approaches targeting GPUs and domain-specific accelerators (DSAs) with native large-integer support. However, GPU-based approaches tend to be less energy-efficient, while DSA designs incur non-trivial non-recurring engineering. Therefore, our work evaluates the potential for RISC-V in HPC and explores multi-word arithmetic using RISC-V. We propose a general modeling-based multi-word extension on the RISC-V Vector (RVV) ISA. Furthermore, we develop comprehensive performance models to analyze performance consistency across host vector processing systems with diverse microarchitectural configurations. Our work demonstrates that targeted architectural extensions can further saturate the pipeline by enhancing RVV’s carry-propagation support.
Event Type
Workshop
TimeMonday, 17 November 202511:10am - 11:30am CST
Location242