Presentation
Range Search on Heterogeneous Systems with Processing-in-Memory Architecture
DescriptionThe growing volume of data in high performance computing (HPC) has made spatial query processing increasingly challenging due to high data transfer costs and limited memory bandwidth. To address these bottlenecks and reduce energy wasted on data movement, this work explores processing-in-memory (PIM) systems by executing range queries directly inside memory chips. Unlike prior PIM studies centered on linear scans or hash-based queries, this work is the first to map R-tree range queries onto PIM hardware. The proposed broadcast-based method constructs the R-tree bottom-up on the CPU, broadcasts top levels to UPMEM DPUs (DRAM processing units) for global filtering, and distributes lower levels for parallel batched queries in a CPU–DPU system. On the Lakes dataset (8M rectangles), it achieves 8× speedup over sequential CPU baselines, with synthetic benchmarks up to 10.9×. These results highlight the promise of PIM-based heterogeneous systems for scalable, energy-efficient spatial query processing in HPC workloads.
Event Type
Research and ACM SRC Posters
TimeThursday, 20 November 20258:00am - 5:00pm CST
LocationSecond Floor Atrium
Archive
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