Presentation
Accelerating Scientific Workflows with LLM-Driven Compiler Optimizations for Generated High-Performance Hardware
DescriptionThe optimization of computation kernels is central to high performance computing, directly impacting applications from scientific computing to artificial intelligence (AI). In experimental workflows with high-throughput or streaming data, software-only execution often becomes a bottleneck, motivating custom hardware accelerators. Field-programmable gate arrays and application-specific integrated circuits excel at these workloads by exploiting parallelism, pipelining, and low latency. Yet, mapping optimized kernels to hardware with high-level synthesis (HLS) requires significant manual effort. To address this, we propose a large language model (LLM)-driven optimization approach. Our method leverages the MLIR compiler infrastructure and modern LLMs’ capability to synthesize code to create tailored optimization strategies for hardware targets through HLS. This approach achieved 2.7x speedup for an electron energy loss spectroscopy autoencoder model targeting the Virtex UltraScale+. These results show that LLM-driven optimization offers a low-effort, high-performance alternative to manual workflows, paving the way for agentic AI in compilers and high performance computing.
Event Type
Research and ACM SRC Posters
TimeThursday, 20 November 20258:00am - 5:00pm CST
LocationSecond Floor Atrium
Archive
view