Presentation
Next Vector Project Based on Proven NEC Vector and RISC-V Architecture
SessionHardware and Architecture
DescriptionThe Next Vector Project by NEC addresses the growing challenges in high performance computing (HPC), such as energy efficiency, scalability, and accessibility. Building on the proven SX-Aurora TSUBASA vector architecture, the project integrates the open-standard RISC-V instruction set to foster innovation and collaboration. NEC (a Japanese IT company) partners with Openchip & Software Technologies in Spain to co-develop this next-generation processor system. The initiative emphasizes not only advanced hardware but also a robust software ecosystem, including compiler development and user-friendly programming tools. The goal is to make powerful vector computing accessible to a broader range of users, from HPC experts to domain scientists. The presentation outlines current HPC challenges, showcases the benefits of vector computing, and details the technical and collaborative aspects of the Next Vector Project, including its roadmap and specifications.
Event Type
Exhibitor Forum
TimeThursday, 20 November 202510:30am - 11:00am CST
Location130
Hardware and Architecture